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Espressif Systems /ESP32-S3 /DMA /OUT_INT_ENA_CH0

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Interpret as OUT_INT_ENA_CH0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OUT_DONE)OUT_DONE 0 (OUT_EOF)OUT_EOF 0 (OUT_DSCR_ERR)OUT_DSCR_ERR 0 (OUT_TOTAL_EOF)OUT_TOTAL_EOF 0 (OUTFIFO_OVF_L1)OUTFIFO_OVF_L1 0 (OUTFIFO_UDF_L1)OUTFIFO_UDF_L1 0 (OUTFIFO_OVF_L3)OUTFIFO_OVF_L3 0 (OUTFIFO_UDF_L3)OUTFIFO_UDF_L3

Description

Interrupt enable bits of Tx channel 0

Fields

OUT_DONE

The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
OUT_EOF

The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
OUT_DSCR_ERR

The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
OUT_TOTAL_EOF

The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
OUTFIFO_OVF_L1

The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
OUTFIFO_UDF_L1

The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
OUTFIFO_OVF_L3

The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
OUTFIFO_UDF_L3

The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data